A monolithic integrated circuit is a combination of interconnected circuit elements inseparably associated on or within a continuous substrate. Typically, the circuit elements are conventional components--transistors, diodes, capacitors, and resistors--fabricated in situ within or on a single crystal of semiconductor material with the capability of performing a complete electronic circuit function.
In practice, an integrated circuit is designed in a top-down method by first designing a logic level drawing and a transistor level drawing. These drawings then are used to design the more detailed integrated circuit layout, which shows the IC layers (i.e., metal, polysilicon, active, and the ways they interrelate to form transistor gates, wires, contact points, etc.). The integrated circuit layout, often referred to as "geometry," is used to generate the integrated circuit tooling, which is a series of masks, each representing a layer for the integrated circuit. The tooling is then used by manufacturers to fabricate an integrated circuit.
Typically, monolithic integrated circuits are fabricated by a process of photolithography, doping, and material deposition. Photolithography is any technique whereby light or other electromagnetic rays are shown through a mask to create a pattern on a silicon wafer coated with a photosensitive film. Doping includes those techniques for treating the exposed areas in the pattern to take on n- or p-type characteristics to form components of transistors and diodes. "Material deposition" refers to the growth or deposit of photoresist, insulating oxide, metal, polysilicon, and other materials that form the topology of the circuit.
In one method for fabricating an integrated circuit, a layer of photoresistive material is deposited on a semiconductor wafer. A mask for the integrated circuit is then placed over the layer of photoresistive material and light is shown through the mask to activate parts of the photoresistive material, thereby leaving a predetermined pattern of conductors on the wafer and exposed areas of the wafer between the conductors. Transistors and diodes are then formed by doping portions the exposed areas of the wafer with a chemical doping agent. A second mask can then be used to generate another pattern of conductors and exposed areas which are, once again, doped. Additional doping layers may also be used. After each doping step, the photoresistive material is chemically removed from the wafer. When the final doping layer has been completed, a pattern of exposed areas of the wafer is once again formed by exposing a layer of photoresist on the wafer through a mask. A layer of metal or other suitable conductor is then deposited onto portions of the exposed areas of the semiconductor wafer to form the desired interconnections between components on the wafer. Though there are many fabrication technologies, fabrication techniques, and integrated circuit materials, fabricating the design for the integrated circuit through one or more masks is used consistently.
Depending on the fabrication technologies and techniques, and the materials used, different configuration constraints apply. These constraints are commonly referred to as "geometric design rules" or "design rules." Design rules include, for example, specifications for minimum spacing between transistors and minimum separation between conductors to prevent shorting, specifications for minimum metal width, and specifications for maximum metal heights and slopes of walls which form metal junctions.
With the continued improvement of fabrication technologies and techniques and the development of new materials used in defining electronic circuits, design rules are changing to allow for smaller and smaller spacings between materials on an integrated circuit and to allow smaller and smaller substrate areas. Thus design rules may change during the development process of any particular circuits. Because increases in the die size of a mask by 15% typically result in a doubling of the cost of an integrated circuit, minimal substrate areas are desired.
One of the most commonly used methods for changing integrated circuit layouts to account for these design rules or changes in these design rules is called the "manual compaction method." If the substrate area specification is reduced during the middle of the design process, the designer, using the manual compaction method, manually varies each of the spacings shown in the integrated circuit layout. Because the relative movement of any component impacts the spacing of all adjacent components, the adjacent components may also have to be moved. As a result, this manual process is very tedious and time-consuming. It consequently limits the circuit complexity that integrated circuits designed in this manner can achieve, and precludes the development of a market for most custom-integrated circuits.
Another method used to make changes in integrated circuit layouts is the virtual grid compaction method, developed at Bell Laboratories. In this method, a virtual grid of typical worst-case component spacing is defined and the circuit components are relatively positioned on the grid using an automatic post-processing algorithm. Each grid line is then sequentially moved closer to another grid line until a design rule is violated. A problem with this approach is that the design rule constraint must apply to the entire grid line, thereby impacting neighboring devices which may have allowed for less spacing and thus more compaction.
Typically, the manual compaction processes have been the expensive and time-consuming processes used for minimizing the area and cost of an integrated circuit. A turnaround time of six months or more has been common. There has long been a need for a versatile and simple compaction method that can accommodate the various design rules and constraints from different fabrication techniques and materials and achieve compaction results comparable to manual methods.